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zxc
- 小写字母变大写字母（汇编语言实现） (2008-05-14 21:57:52) 标签：杂谈 DATA SEGMENT PMT1 DB INPUT Small letter : ,0AH,0DH, $ STR1 DB 40H,0,40H DUP(0) PMT2 DB 0AH,0DH, Display capital letter : ,0AH,0DH STR2 DB 40H DUP(0), $
dcpwm
- 直流电机的开环控制，包括初始化设施定时器，设置PWM的脉冲宽度和设定方向，定时器中断处理程序等-Open-loop DC motor control, including the initialization facilities timer, set the PWM pulse width and set a direction for the timer interrupt handling procedures
systempwm
- 直流电机的闭环控制，包括初始化设置定时器，初始化设置设定INT0的工作方式，设置PWM的脉冲宽度和设定方向等-Closed-loop DC motor control, including the initialization settings timer, initialization settings set INT0 work, set PWM pulse width and set the direction
ad421
- 4~20mA电流环输出式数模转换器AD421的基本接线-4 ~ 20mA current loop output DAC AD421 basic wiring
loop
- 编程实现素数环的程序，很有意思，程序不是很复杂，很容易看懂。-Programming prime ring procedures, very interesting, is not a very complicated procedure, it is easy to understand.
34
- 1．求两个数的最大公约数 2. n! 3. 循环计数器 4．堆栈 5．实现大数的加减运算-1. The common denominator for both the number of 2. N! 3. Loop counter 4. Stack 5. The realization of addition and subtraction of large numbers of computing
2407SVPWM
- 三相交流异步电动机的开环源码，包括所有文件-Three-phase AC induction motor open-loop source, including all documents
sfs
- DW 256 DUP(?) STACK1 ENDS DDATA SEGMENT MES1 DB The least number is:$ MES2 DB 0AH,0DH, The largest number is:$ NUMB DB 0D9H,07H,8BH,0C5H,0EBH,04H,9DH,0F9H DDATA ENDS CODE SEGMENT ASSUME CS:CODE
timer_trigger_adc_PLL_SUCCESS
- DSP2407定时器触发ADC，并且进行软件锁相环的实现。-DSP2407 timer to trigger ADC, and the realization of a software phase-locked loop.
CE034_CAN_Loopback
- PIC18fXX can源程序,回环控制的代码,-PIC18fXX can source, loop control code,
SVPWM
- Three-phase AC induction motor SVPWM open-loop speed control (software method)
newDPLLdesign
- 使用VHDL语言进行数字锁相环的设计，pdf格式，可以打开-The use of VHDL language design of digital phase-locked loop, pdf format, you can open
NewWayOfDPLLdesign
- 使用VHDL语言进行设计DPLL（数字锁相环）的相关文件-The use of VHDL language design DPLL (digital phase-locked loop) of the relevant documents
DPLL2
- 全数字锁相环电路的研制，使用的是VHDL语言 -All-digital phase-locked loop circuit development, using the VHDL language
DPLL(VHDL)
- 使用VHDL语言进行的数字锁相环的设计，里面有相关的文件，可以使用MUX+PLUS打开-The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
GSMreaserch
- 短信的发送需要GSM模块和处理器协作完成,GSM模块与ARM处理器通过串口连接,处理器向串口发送接收AT命令与 GSM模块形成通信回路。-Send text messages GSM modules and processors need to be completed in collaboration, GSM module and the ARM processor through the serial port connect
gaf_pid
- 我们知道，PID控制器各参数对系统的影响是；增大开环比例系数 ，一般将加快系统的影响速度，在有静差的情况下则有利于减小静差；但过大的比例系数又会加大系统超调，甚至产生振荡，使系统不稳定。-We know that, PID controller parameters on the system is increasing the proportion of open-loop coefficients, the general wil
gaf_pid2
- 我们知道，PID控制器各参数对系统的影响是；增大开环比例系数 ，一般将加快系统的影响速度，在有静差的情况下则有利于减小静差；但过大的比例系数又会加大系统超调，甚至产生振荡，使系统不稳定。-We know that, PID controller parameters on the system is increasing the proportion of open-loop coefficients, the general wil
pid_zen_ding
- 我们知道，PID控制器各参数对系统的影响是；增大开环比例系数 ，一般将加快系统的影响速度，在有静差的情况下则有利于减小静差；但过大的比例系数又会加大系统超调，甚至产生振荡，使系统不稳定。-We know that, PID controller parameters on the system is increasing the proportion of open-loop coefficients, the general wil
FPGA444555443
- 基于FPGA的全数字锁相环设计,内有设计过程和设计思想-FPGA-based all-digital phase-locked loop design, with the design process and design thinking