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USB 2.0 IP Core
- USB20的IP CORE,可以直接用在SOPC下，自动完成全部的枚举，只需修改枚举参数即可！-USB20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
8-bit-mcu-ip-core-design-and-verification
- 万方数据库中载的，关于IP核设计和验证方面的论文-popular database containing, for the IP core design and certification papers
PS2-IP-CORE-VHDL
- 一个PS2 IP CORE(VHDL) for FPGA
USB 1.1 IP-CORE和设计范例 VHDL源代码
- USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
IP core
- VHDL ip core的设计，软核的设计方法-VHDL core of the design, soft-core design
turbo码 IP core
- turbo码 IP core, VHDL编写，Altera公司的，用于信道编码中turbo码的译码
USB 1.1 IP-CORE和设计范例 VHDL源代码
- USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
IP core
- VHDL ip core的设计，软核的设计方法-VHDL core of the design, soft-core design
FFT变换的IP核的源代码 VHDL~
- FFT变换的IP核的源代码 VHDL~-FFT IP core of the source code for VHDL ~
发布15个Altera的IP的源码
- ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.-Altera FPGA IP core of the source code for the use of Altera FPGA design to provide the relevant information.
MC8051 IP Core
- 8051的IP软核，使用硬件描述语言编写，可以下载到FPGA/CPLD中作为片上系统的处理器-8051 IP soft-core, the use of hardware descr iption language can be downloaded to the FPGA/CPLD as a system-on-chip processor
USB 2.0 IP Core
- USB20的IP CORE,可以直接用在SOPC下，自动完成全部的枚举，只需修改枚举参数即可！-USB20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
8-bit-mcu-ip-core-design-and-verification
- 万方数据库中载的，关于IP核设计和验证方面的论文-popular database containing, for the IP core design and certification papers
PS2-IP-CORE-VHDL
- 一个PS2 IP CORE(VHDL) for FPGA-A PS2 IP CORE (VHDL) for FPGA
15-IP-core
- 15个免费的IP核 IP核源代码 -15 IP cores
QuartusII-free-of-charge-to-use-IP-Core
- 本文详细的介绍了QuartusII中免费IP核的使用方法-This paper introduces QuartusII free of charge to use IP Core
ethernet10-100M-IP-core
- 以太网10-100M IP核Verilog源码，可综合-Ethernet 10-100M IP core Verilog source code can be integrated
USB-1.1-IP-CORE-VHDL
- USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code
vhdl-fft-core
- FFT ip core，fft信号处理模块， VHDL语言编写-FFT ip core
pg137-axi-usb2-device(xilinx USB ip core)
- xilinx USB ip 核使用说明文档，接口完全和usb3320接口一致(Xilinx USB IP core usage instructions document, the interface is completely consistent with the usb3320 interface)