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vhdl3
- 介绍一种基于VHDL 语言的全数字锁相环实现方法， 并用这种方法在FPGA 中实现了全 数字锁相环，作为信号解调的位同步模块。-Introduction of a language based on VHDL implementations of DPLL, and this method is implemented in the FPGA digital phase locked loop, as the signal demo
dpll_ieee
- implementation of dpll.a technique used by ieee.
mydesign_DPLL
- 实现了数字锁相环设计，可以用于信号的时钟提取供本地时钟使用-the design introduced a method to use DPLL,we can get the local clock from the signal
DPLL
- 数字锁相环频率合成器的设计,鉴相器、环路滤波器、数控振荡器、反馈分频器-Digital PLL frequency synthesizer, phase detector, loop filter, NCO, feedback divider
DPLL
- 模数转换的数字锁相环，代码中有详细的说明-digital phase lock loop
Untitled8
- source code and matlab code for second order dpll in digital signal processor
bit-sychronization
- 全数字锁相环实现位同步，通过3个触发器实现码元的边沿提取。基带码采用M序列仿真。-DPLL to achieve bit synchronization, achieved through three trigger symbol of the edge extraction. Baseband codes using M-sequence simulation.
digital_pll_cicc_tutorial_perrott
- Very good dpll tutorial.
VHDL-FPGA-DLL
- 自动检测中英文中译英英译中百度翻译 翻译结果（中 > 英）复制结果 A VHDL language based on all digital phase-locked loop DPLL VHDL realization-自动检测中英文中译英英译中百度翻译 翻译结果（中 > 英）复制结果 A VHDL language based on all digital phase-locked loop
VHDL-FPGA-ALL-digital-DDLL
- VHDL 全数字锁相环 ise7.1i环境实现 内有代码 和时域仿真结果-A VHDL language based on all digital phase-locked loop DPLL VHDL realization
DPLL
- 二阶锁相环仿真，输入频偏为阶跃信号时的仿真-pll simulation
APDLL
- 数字锁相环的FPGA设计与实现，用maxplus2实现的-DPLL FPGA design and implementation, with maxplus2 achieve
fm_txrx_simple
- dpll demoudulation in FM
PhasePLockedPLoop
- pll的封装模块主要有cppll，dpll,linearpll,powerpll.-Encapsulation of a PLL module,include:cppll，dpll,linearpll,powerpll and so on.
FdplllzipP
- ＦＰＧＡ实现全数字锁相环，运用硬件描述评议议verilog HDL，顶层文件ＤＰＬＬ．Ｖ -FPGA implementation of DPLL, the use of hardware descr iption council meeting Verilog HDL top-level file DPLL is. V
sfdppllli
- 简单易懂的可配置dpll的VHDL代码。用于时钟恢复后的相位抖动的的滤波有非常好的效果， 而且能参数化配置pll的级数。 已通过测试。 -Straightforward configuration VHDL code dpll. Very good results for the clock recovery phase jitter filtering, and can be parameterized configuration
759744
- dpll源代码，实现基本功能，具体BUG需自己修改-dpll unit
DPLL
- 90度锁定的数字锁相环的设计的VHDL源代码-The VHDL code of Digital Phase-Locked Loop Based on CPLD
USB1.1-VHDL
- USB PHY RX DPLL This source file may be used and distributed without restriction provided that this copyright statement is not removed from the file and that any derivative work contains the original copyright notice and
dpll
- Simulink all digital p-Simulink all digital plll