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4bits_alu
- 实现4位加减乘除的alu，采用超前进位加法和布斯乘法，代码较为简单。-achieve four of the ALU arithmetic using CLA Bush and multiplication, code more simple.
adder_ahead8bit
- 本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.-using verilog HDL achieve the eight-ahead adder, fully demonstrates the CLA for ordinary Adder and the distinction between.
CLA
- 超前进位加法器得VHDL实现小点资料代码-CLA was a small point of information VHDL code
adder
- 8位超前进位加法器 就是使各位的进位直接由加数和被加数来决定，而不需要依赖低位进位-8-bit CLA is to make your binary direct summand by summand and to decide, rather than to rely on low binary
trueif
- 一个超前进位加法器（及其testbench) .v文件-A CLA (and its testbench). V file
adder_32
- 超前进位加法器是通常数字设计所必备的，本程序为32位超前进位加法器-CLA is usually necessary for digital design, the procedure for 32-bit CLA
16bitCLA
- 基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
adder
- 运用VHDL语言实现四位超前进位加法器。-VHDL language using the four CLA.
CLA.VHDL.CODE
- cla vhdl code with a picture files.
ADDER(2)
- simple 16-bet CLA adder
adder
- 8位cla，采用for结构，可以扩张成32位或者16位-8 cla, used for the structure, you can expand into a 32-bit or 16-bit
4
- simple code based on verilog shifter , cla ,clg , ALU , PC
cla
- a cla coding in verilog
16bit-CLA
- 16 bit carry look ahead adder verilog code
cla-adder
- cla adder code in vhdl
CLA-CCSv3.3
- F28035的DSP，CCS3.3应用环境的配置，可以在一台电脑上同时打开主CPU和CLA的调试界面，对于使用CLA的并且不习惯使用新版ccs4开发环境的用户很有用！-F28035 the DSP, CCS3.3 application environment configuration on a computer at the same time open the main CPU and CLA debug interface, u
CLA-CCSv4.x
- F28035DSP，在CCS4环境下的配置，可以同时调试主CPU和CLA-F28035DSP, in the environment of CCS4 configuration, can debug the main CPU and CLA
32-bit-cla-adder
- This a code that describe 32 bit carry look ahead adder in VHDL(32 bit CLA).-This is a code that describe 32 bit carry look ahead adder in VHDL(32 bit CLA).
Memetic-CLA-PSO
- Memetic CLA PSO: A Hybrid Model for Optimization
CLA
- CLA adder:use vhdl to write the carry-lookahead adder which is a type of adder used in digital logic-CLA adder