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quartusII7.1crack
- quartus_II_7.1的license破解工具，很好用
clkgen
- 用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.
bdf
- 8位加法器的实现，仿真通过，并且包括仿真文件，在quartusii7.1下调试通过
Crack_QII70
- quartusII7.0license解码
DA_FIR
- 基于分布式算法的FPGA实现的FIR滤波器源码，VHDL语言编写的，下载工程文件后可直接在QuartusII7.0上运行。
quartusII7.1crack
- quartus_II_7.1的license破解工具，很好用-quartus_II_7.1
clkgen
- 用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.-CPLD with minimal resources, using Verilog in QuartusII7.1 to achieve the 1280 frequency.
bdf
- 8位加法器的实现，仿真通过，并且包括仿真文件，在quartusii7.1下调试通过-8-bit adder realization, through simulation, and includes simulation document, under the debugger through quartusii7.1
Crack_QII70
- quartusII7.0license解码 -quartusII7.0license decoder
DA_FIR
- 基于分布式算法的FPGA实现的FIR滤波器源码，VHDL语言编写的，下载工程文件后可直接在QuartusII7.0上运行。-Based on Distributed algorithms realize the FIR filter FPGA source code, VHDL language, download the project file can be run directly in QuartusII7.0.
speech
- 用verilog HDL实现自相关算法！ RTL级可综合代码！ 通过modelsim5.6仿真和quartusii7.1综合！-Verilog HDL using auto-correlation algorithm to achieve! RTL-level code can be integrated! Through simulation and modelsim5.6 integrated quartusii7.1!
dds_using_FPGA
- 利用FPGA实现DDS经过编译没有错误。编译环境为QuartusII7.2，该环境集成了IP核，可以提高开发效率。-FPGA realization of the use of DDS compiled no errors. Compiler environment QuartusII7.2, the environment integrated IP core, can improve the development efficien
nios2-flash-programmer
- 开发VHDL的工具 QuartusII7.2_破解.rar-QuartusII7.2
quartusII7.2license(2)
- quartus7.2的license破解，里面有详细说明，简单实用-quartus7.2 to break the license, which has detailed descr iption of simple and practical
seg7led
- 基于quartusII7.2的七段led试验程序，全面，丰富且完全通过功能验证-Led the team respectively quartusII7.2 based on testing procedures, comprehensive, rich and fully functional verification
IIR_Filter
- 一个简要的低通滤波程序IIR Filter QuartusII7-IIR Filter QuartusII7
Crack_QII72
- QuartusII7.2破解文件注册文件-QuartusII7.2 crack file registration documents
SEG7_Timer
- 七段数码管时钟显示的verilog程序，开发环境quartusII7.0-Seven-segment digital tube display clock verilog program development environment quartusII7.0
PWM_LED
- 利用PWM控制LED亮灭的verilog程序，开发环境quartusII7.0-Using PWM control of LED light off a verilog program development environment quartusII7.0
clock
- 基于Verilog的数字时钟的源代码 用quartusII7.2软件仿真通过-Verilog-based digital clock