文件名称:RISC
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hrisc cpu，为何只有vhdl选择呢？大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
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下载文件列表
RISC
....\interface
....\.........\ps2
....\.........\...\ps2_soc1
....\RISC16f84
....\.........\auto_baud_with_tracking.v
....\.........\b13b_safe_12_05_02_cleanedup.zip
....\.........\build_13.ucf
....\.........\reg_4_pack_clrset.v
....\.........\reg_8_pack.v
....\.........\risc16f84_clk2x.v
....\.........\rs232_syscon.v
....\.........\serial.v
....\.........\square_wave_dds.v
....\.........\test8.232
....\.........\TEST8.C
....\.........\TEST8.HEX
....\.........\TEST8.LST
....\.........\TEST8.SYM
....\.........\top.v
....\.........\transcript
....\.........\vga_128_by_92.v
....\.........\xilinx_block_ram_3_3.v
....\.........\xilinx_block_ram_8_16.v
....\interface
....\.........\ps2
....\.........\...\ps2_soc1
....\RISC16f84
....\.........\auto_baud_with_tracking.v
....\.........\b13b_safe_12_05_02_cleanedup.zip
....\.........\build_13.ucf
....\.........\reg_4_pack_clrset.v
....\.........\reg_8_pack.v
....\.........\risc16f84_clk2x.v
....\.........\rs232_syscon.v
....\.........\serial.v
....\.........\square_wave_dds.v
....\.........\test8.232
....\.........\TEST8.C
....\.........\TEST8.HEX
....\.........\TEST8.LST
....\.........\TEST8.SYM
....\.........\top.v
....\.........\transcript
....\.........\vga_128_by_92.v
....\.........\xilinx_block_ram_3_3.v
....\.........\xilinx_block_ram_8_16.v