压缩包 : 39709595codes.rar 列表
codes\20061125113331.doc
codes\ASIC design lecture.ppt
codes\Ethernet IP core Verilog .rar
codes\fpga实现jpeg Verilog源代码 .rar
codes\Linux 内核0.11 详细注释.pdf
codes\Linux内核0.11详细注释.rar
codes\miller解码器设计(050710)\~WRL0562.tmp
codes\miller解码器设计(050710)\~WRL0958.tmp
codes\miller解码器设计(050710)\~WRL2233.tmp
codes\miller解码器设计(050710)\~WRL3085.tmp
codes\miller解码器设计(050710)\关于本题.txt
codes\miller解码器设计(050710)\密勒解码器设计文档.doc
codes\miller解码器设计(050710)\源代码\decode.v
codes\miller解码器设计(050710)\源代码\decode_tb.v
codes\miller解码器设计(050710)\源代码\miller_decode.v
codes\miller解码器设计(050710)\源代码\miller_decode_tb.v
codes\miller解码器设计(050710)\源代码\Signal_detect.v
codes\miller解码器设计(050710)\源代码\Signal_detect_tb2.v
codes\miller解码器设计(050710)\第一题.doc
codes\miller解码器设计(050710)\结果波形\decode.bmp
codes\miller解码器设计(050710)\结果波形\miller_decode_1.bmp
codes\miller解码器设计(050710)\结果波形\miller_decode_2.bmp
codes\miller解码器设计(050710)\结果波形\Signal_detect_1.bmp
codes\miller解码器设计(050710)\结果波形\Signal_detect_2.bmp
codes\miller解码器设计(050710)\结果波形\Thumbs.db
codes\modelsim使用教程.pdf
codes\PCI总线仲裁参考设计Verilog代码.rar
codes\ps2 driver\ps2_driver.v
codes\PS2 驱动代码.rar
codes\Verilog HDL Test Bench入门.rar
codes\Verilog program examples\chap10\acc.acf
codes\Verilog program examples\chap10\acc.hif
codes\Verilog program examples\chap10\acc.v
codes\Verilog program examples\chap10\accn.v
codes\Verilog program examples\chap10\add8.v
codes\Verilog program examples\chap10\adder8.v
codes\Verilog program examples\chap10\block1.v
codes\Verilog program examples\chap10\block2.v
codes\Verilog program examples\chap10\block3.v
codes\Verilog program examples\chap10\block4.v
codes\Verilog program examples\chap10\control.v
codes\Verilog program examples\chap10\fsm.v
codes\Verilog program examples\chap10\longframe1.v
codes\Verilog program examples\chap10\longframe2.v
codes\Verilog program examples\chap10\pipeline.v
codes\Verilog program examples\chap10\reg8.v
codes\Verilog program examples\chap10\resource1.v
codes\Verilog program examples\chap10\resource2.v
codes\Verilog program examples\chap11\account.v
codes\Verilog program examples\chap11\clock.v
codes\Verilog program examples\chap11\count10.v
codes\Verilog program examples\chap11\fre_ctrl.v
codes\Verilog program examples\chap11\latch_16.v
codes\Verilog program examples\chap11\paobiao.v
codes\Verilog program examples\chap11\sell.v
codes\Verilog program examples\chap11\song.v
codes\Verilog program examples\chap11\traffic.v
codes\Verilog program examples\chap12\add_ahead.v
codes\Verilog program examples\chap12\add_bx.v
codes\Verilog program examples\chap12\add_jl.v
codes\Verilog program examples\chap12\add_tree.v
codes\Verilog program examples\chap12\correlator.v
codes\Verilog program examples\chap12\crc.v
codes\Verilog program examples\chap12\cycle.v
codes\Verilog program examples\chap12\decoder1.v
codes\Verilog program examples\chap12\decoder2.v
codes\Verilog program examples\chap12\fir.v
codes\Verilog program examples\chap12\linear.v
codes\Verilog program examples\chap12\mult.v
codes\Verilog program examples\chap12\mult4x4.v
codes\Verilog program examples\chap3\adder4.acf
codes\Verilog program examples\chap3\adder4.hif
codes\Verilog program examples\chap3\adder4.ndb
codes\Verilog program examples\chap3\adder4.v
codes\Verilog program examples\chap3\adder_tp.v
codes\Verilog program examples\chap3\aoi.v
codes\Verilog program examples\chap3\count4.v
codes\Verilog program examples\chap3\count4_tp.v
codes\Verilog program examples\chap5\adder.v
codes\Verilog program examples\chap5\adder16.v
codes\Verilog program examples\chap5\alu.v
codes\Verilog program examples\chap5\block.v
codes\Verilog program examples\chap5\buried_ff.v
codes\Verilog program examples\chap5\compile.v
codes\Verilog program examples\chap5\count.v
codes\Verilog program examples\chap5\count60.v
codes\Verilog program examples\chap5\decode4_7.v
codes\Verilog program examples\chap5\loop1.v
codes\Verilog program examples\chap5\loop2.v
codes\Verilog program examples\chap5\loop3.v
codes\Verilog program examples\chap5\mult_for.v
codes\Verilog program examples\chap5\mult_repeat.v
codes\Verilog program examples\chap5\mux21_1.v
codes\Verilog program examples\chap5\mux21_2.v
codes\Verilog program examples\chap5\mux4_1.v
codes\Verilog program examples\chap5\mux_casez.v
codes\Verilog program examples\chap5\non_block.v
codes\Verilog program examples\chap5\test.v
codes\Verilog program examples\chap5\voter7.v
codes\Verilog program examples\chap5\wave1.v
codes\Verilog program examples\chap5\wave2.v
codes\Verilog program examples\chap6\alutask.v
codes\Verilog program examples\chap6\alu_tp.v
codes\Verilog program examples\chap6\code_83.v
codes\Verilog program examples\chap6\count.v
codes\Verilog program examples\chap6\funct.v
codes\Verilog program examples\chap6\funct_tp.v
codes\Verilog program examples\chap6\paral1.v
codes\Verilog program examples\chap6\paral2.v
codes\Verilog program examples\chap6\serial1.v
codes\Verilog program examples\chap6\serial2.v
codes\Verilog program examples\chap7\add4_1.v
codes\Verilog program examples\chap7\add4_2.v
codes\Verilog program examples\chap7\add4_3.v
codes\Verilog program examples\chap7\count4.v
codes\Verilog program examples\chap7\full_add1.v
codes\Verilog program examples\chap7\full_add2.v
codes\Verilog program examples\chap7\full_add3.v
codes\Verilog program examples\chap7\full_add4.v
codes\Verilog program examples\chap7\full_add5.v
codes\Verilog program examples\chap7\half_add1.v
codes\Verilog program examples\chap7\half_add2.v
codes\Verilog program examples\chap7\half_add3.v
codes\Verilog program examples\chap7\half_add4.v
codes\Verilog program examples\chap7\mux2_1a.v
codes\Verilog program examples\chap7\mux2_1b.v
codes\Verilog program examples\chap7\mux2_1c.v
codes\Verilog program examples\chap7\mux4_1a.v
codes\Verilog program examples\chap7\mux4_1b.v
codes\Verilog program examples\chap7\mux4_1c.v
codes\Verilog program examples\chap7\mux4_1d.v
codes\Verilog program examples\chap8\add8_tp.v
codes\Verilog program examples\chap8\carry_udp.v
codes\Verilog program examples\chap8\carry_udpx1.v
codes\Verilog program examples\chap8\carry_udpx2.v
codes\Verilog program examples\chap8\count8_tp.v
codes\Verilog program examples\chap8\delay.v
codes\Verilog program examples\chap8\dff.v
codes\Verilog program examples\chap8\dff_udp.v
codes\Verilog program examples\chap8\latch.v
codes\Verilog program examples\chap8\mult_tp.v
codes\Verilog program examples\chap8\mux31.v
codes\Verilog program examples\chap8\mux_tp.v
codes\Verilog program examples\chap8\random_tp.v
codes\Verilog program examples\chap8\rom.v
codes\Verilog program examples\chap8\test1.v
codes\Verilog program examples\chap8\test2.v
codes\Verilog program examples\chap8\time_dif.v
codes\Verilog program examples\chap9\bidir.v
codes\Verilog program examples\chap9\bidir2.v
codes\Verilog program examples\chap9\code_83.v
codes\Verilog program examples\chap9\decode47.v
codes\Verilog program examples\chap9\decoder_38.v
codes\Verilog program examples\chap9\dff.v
codes\Verilog program examples\chap9\dff1.v
codes\Verilog program examples\chap9\dff2.v
codes\Verilog program examples\chap9\encoder8_3.v
codes\Verilog program examples\chap9\gate1.v
codes\Verilog program examples\chap9\gate2.v
codes\Verilog program examples\chap9\gate3.v
codes\Verilog program examples\chap9\jk_ff.v
codes\Verilog program examples\chap9\johnson.v
codes\Verilog program examples\chap9\latch_1.v
codes\Verilog program examples\chap9\latch_2.v
codes\Verilog program examples\chap9\latch_8.v
codes\Verilog program examples\chap9\mac.v
codes\Verilog program examples\chap9\mac_tp.v
codes\Verilog program examples\chap9\map_lpm_ram.v
codes\Verilog program examples\chap9\mpc.v
codes\Verilog program examples\chap9\mpc_tp.v
codes\Verilog program examples\chap9\mux_case.v
codes\Verilog program examples\chap9\mux_if.v
codes\Verilog program examples\chap9\parity.v
codes\Verilog program examples\chap9\ram256x8.v
codes\Verilog program examples\chap9\reg8.v
codes\Verilog program examples\chap9\rom.v
codes\Verilog program examples\chap9\serial_pal.v
codes\Verilog program examples\chap9\shifter.v
codes\Verilog program examples\chap9\tri_1.v
codes\Verilog program examples\chap9\tri_2.v
codes\Verilog program examples\chap9\updown_count.v
codes\Verilog program examples\examples.pdf
codes\Verilog 程序例子.rar
codes\VGALCD 控制器IP .rar
codes\vhdl.pdf
codes\加密解密.rar
codes\数字集成电路设计从HDL到版图 .rar
codes\用verilog设计密勒解码器  .rar
codes\miller解码器设计(050710)\源代码
codes\miller解码器设计(050710)\结果波形
codes\Verilog program examples\chap10
codes\Verilog program examples\chap11
codes\Verilog program examples\chap12
codes\Verilog program examples\chap3
codes\Verilog program examples\chap5
codes\Verilog program examples\chap6
codes\Verilog program examples\chap7
codes\Verilog program examples\chap8
codes\Verilog program examples\chap9
codes\miller解码器设计(050710)
codes\ps2 driver
codes\Verilog program examples
codes