文件名称:06_lcd7_touch
介绍说明－－下载内容均来自于网络，请自行研究使用
基于7Z010的触摸屏驱动程序.开发板使用的是Xilinx公司的Zynq7000 系列的芯片， 型号为XC7Z010-1CLG400C，
400 个引脚的 FBGA 封装。 ZYNQ7000 芯片可分成处理器系统部分 Processor System（PS）
和可编程逻辑部分 Programmable Logic（PL）。 在 AX7010 开发板上，ZYNQ7000 的 PS
部分和 PL 部分都搭载了丰富的外部接口和设备，方便用户的使用和功能验证。-Touch screen driver based on 7z010
400 个引脚的 FBGA 封装。 ZYNQ7000 芯片可分成处理器系统部分 Processor System（PS）
和可编程逻辑部分 Programmable Logic（PL）。 在 AX7010 开发板上，ZYNQ7000 的 PS
部分和 PL 部分都搭载了丰富的外部接口和设备，方便用户的使用和功能验证。-Touch screen driver based on 7z010
(系统自动生成,下载前可以参看下载内容)
下载文件列表
06_lcd7_touch\lcd7_touch.cache\ip\657c7237c2f35d0d\657c7237c2f35d0d.xci
.............\................\..\................\u_ila_0_CV.dcp
.............\................\..\7d0f03ed9dc6c806\7d0f03ed9dc6c806.xci
.............\................\..\................\dbg_hub_CV.dcp
.............\................\wt\java_command_handlers.wdf
.............\................\..\project.wpc
.............\................\..\synthesis.wdf
.............\................\..\synthesis_details.wdf
.............\................\..\webtalk_pa.xml
.............\...........hw\hw_1\hw.xml
.............\.............\lcd7_touch.lpr
.............\...........ip_user_files\bd\system\hdl\system.v
.............\........................\..\......\ip\system_auto_pc_0\sim\system_auto_pc_0.v
.............\........................\..\......\..\...............1\sim\system_auto_pc_1.v
.............\........................\..\......\..\...............2\sim\system_auto_pc_2.v
.............\........................\..\......\..\...............3\sim\system_auto_pc_3.v
.............\........................\..\......\..\...............4\sim\system_auto_pc_4.v
.............\........................\..\......\..\........xis_subset_converter_0_0\axis_subset_converter_v1_1\hdl\verilog\axis_subset_converter_v1_1_axis_subset_converter_system_axis_subset_converter_0_0.v
.............\........................\..\......\..\................................\..........................\...\.......\axis_subset_converter_v1_1_tdata_remap_system_axis_subset_converter_0_0.v
.............\........................\..\......\..\................................\..........................\...\.......\axis_subset_converter_v1_1_tdest_remap_system_axis_subset_converter_0_0.v
.............\........................\..\......\..\................................\..........................\...\.......\axis_subset_converter_v1_1_tid_remap_system_axis_subset_converter_0_0.v
.............\........................\..\......\..\................................\..........................\...\.......\axis_subset_converter_v1_1_tkeep_remap_system_axis_subset_converter_0_0.v
.............\........................\..\......\..\................................\..........................\...\.......\axis_subset_converter_v1_1_tlast_remap_system_axis_subset_converter_0_0.v
.............\........................\..\......\..\................................\..........................\...\.......\axis_subset_converter_v1_1_tstrb_remap_system_axis_subset_converter_0_0.v
.............\........................\..\......\..\................................\..........................\...\.......\axis_subset_converter_v1_1_tuser_remap_system_axis_subset_converter_0_0.v
.............\........................\..\......\..\................................\sim\system_axis_subset_converter_0_0.v
.............\........................\..\......\..\.........._dynclk_0_1\sim\system_axi_dynclk_0_1.vhd
.............\........................\..\......\..\...........gpio_0_0\sim\system_axi_gpio_0_0.vhd
.............\........................\..\......\..\...........iic_0_0\sim\system_axi_iic_0_0.vhd
.............\........................\..\......\..\...........vdma_0_0\sim\system_axi_vdma_0_0.vhd
.............\........................\..\......\..\.......processing_system7_0_0\sim\system_processing_system7_0_0.v
.............\........................\..\......\..\.......rgb2dvi_0_2\sim\system_rgb2dvi_0_2.vhd
.............\........................\..\......\..\........st_processing_system7_0_100M_2\sim\system_rst_processing_system7_0_100M_2.vhd
.............\........................\..\......\..\.................................40M_1\sim\system_rst_processing_system7_0_140M_1.vhd
.............\........................\..\......\..\.......util_vector_logic_0_0\sim\system_util_vector_logic_0_0.vhd
.............\........................\..\......\..\.......v_axi4s_vid_out_0_0\demo_tb\tb_system_v_axi4s_vid_out_0_0.v
.............\........................\..\......\..\..........................\sim\system_v_axi4s_vid_out