文件名称:DDS
介绍说明－－下载内容均来自于网络，请自行研究使用
基于FPGA完成2001年电子设计竞赛直接数字频率合成器，有FPGA部分、MSP430程序以及相互通信的程序，完成题目全部要求-FPGA-based Electronic Design Competition 2001 complete direct digital frequency synthesizer, there is part of the program FPGA, MSP430 procedures and communicate with each other, to complete all the requirements of the subject
(系统自动生成,下载前可以参看下载内容)
下载文件列表
程序
....\FPGA_module
....\...........\EDA_DDS_4
....\...........\.........\db
....\...........\.........\..\altsyncram_04f1.tdf
....\...........\.........\..\altsyncram_0ob1.tdf
....\...........\.........\..\altsyncram_30f1.tdf
....\...........\.........\..\altsyncram_4jc1.tdf
....\...........\.........\..\altsyncram_5ne1.tdf
....\...........\.........\..\altsyncram_7nb1.tdf
....\...........\.........\..\altsyncram_80f1.tdf
....\...........\.........\..\altsyncram_8je1.tdf
....\...........\.........\..\altsyncram_96c1.tdf
....\...........\.........\..\altsyncram_bse1.tdf
....\...........\.........\..\altsyncram_cab1.tdf
....\...........\.........\..\altsyncram_cfc1.tdf
....\...........\.........\..\altsyncram_fjb1.tdf
....\...........\.........\..\FPGA_DDS_4.asm.qmsg
....\...........\.........\..\FPGA_DDS_4.asm.rdb
....\...........\.........\..\FPGA_DDS_4.asm_labs.ddb
....\...........\.........\..\FPGA_DDS_4.cbx.xml
....\...........\.........\..\FPGA_DDS_4.cmp.bpm
....\...........\.........\..\FPGA_DDS_4.cmp.cbp
....\...........\.........\..\FPGA_DDS_4.cmp.cdb
....\...........\.........\..\FPGA_DDS_4.cmp.ecobp
....\...........\.........\..\FPGA_DDS_4.cmp.hdb
....\...........\.........\..\FPGA_DDS_4.cmp.kpt
....\...........\.........\..\FPGA_DDS_4.cmp.logdb
....\...........\.........\..\FPGA_DDS_4.cmp.rdb
....\...........\.........\..\FPGA_DDS_4.cmp_merge.kpt
....\...........\.........\..\FPGA_DDS_4.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
....\...........\.........\..\FPGA_DDS_4.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
....\...........\.........\..\FPGA_DDS_4.db_info
....\...........\.........\..\FPGA_DDS_4.eco.cdb
....\...........\.........\..\FPGA_DDS_4.eds_overflow
....\...........\.........\..\FPGA_DDS_4.fit.qmsg
....\...........\.........\..\FPGA_DDS_4.fnsim.hdb
....\...........\.........\..\FPGA_DDS_4.fnsim.qmsg
....\...........\.........\..\FPGA_DDS_4.hier_info
....\...........\.........\..\FPGA_DDS_4.hif
....\...........\.........\..\FPGA_DDS_4.lpc.html
....\...........\.........\..\FPGA_DDS_4.lpc.rdb
....\...........\.........\..\FPGA_DDS_4.lpc.txt
....\...........\.........\..\FPGA_DDS_4.map.bpm
....\...........\.........\..\FPGA_DDS_4.map.cdb
....\...........\.........\..\FPGA_DDS_4.map.ecobp
....\...........\.........\..\FPGA_DDS_4.map.hdb
....\...........\.........\..\FPGA_DDS_4.map.kpt
....\...........\.........\..\FPGA_DDS_4.map.logdb
....\...........\.........\..\FPGA_DDS_4.map.qmsg
....\...........\.........\..\FPGA_DDS_4.map_bb.cdb
....\...........\.........\..\FPGA_DDS_4.map_bb.hdb
....\...........\.........\..\FPGA_DDS_4.map_bb.logdb
....\...........\.........\..\FPGA_DDS_4.pre_map.cdb
....\...........\.........\..\FPGA_DDS_4.pre_map.hdb
....\...........\.........\..\FPGA_DDS_4.rtlv.hdb
....\...........\.........\..\FPGA_DDS_4.rtlv_sg.cdb
....\...........\.........\..\FPGA_DDS_4.rtlv_sg_swap.cdb
....\...........\.........\..\FPGA_DDS_4.sgdiff.cdb
....\...........\.........\..\FPGA_DDS_4.sgdiff.hdb
....\...........\.........\..\FPGA_DDS_4.sim.cvwf
....\...........\.........\..\FPGA_DDS_4.sim.hdb
....\...........\.........\..\FPGA_DDS_4.sim.qmsg
....\...........\.........\..\FPGA_DDS_4.sim.rdb
....\...........\.........\..\FPGA_DDS_4.simfam
....\...........\.........\..\FPGA_DDS_4.sld_design_entry.sci
....\...........\.........\..\FPGA_DDS_4.sld_design_entry_dsc.sci
....\...........\.........\..\FPGA_DDS_4.smart_action.txt
....\...........\.........\..\FPGA_DDS_4.sta.qmsg
....\...........\.........\..\FPGA_DDS_4.sta.rdb
....\...........\.........\..\FPGA_DDS_4.sta_cmp.6_slow_1200mv_85c.tdb
....\...........\.........\..\FPGA_DDS_4.syn_hier_info
....\...........\.........\..\FPGA_DDS_4.tiscmp.fast_1200mv_0c.ddb
....\...........\.........\..\FPGA_DDS_4.tiscmp.slow_1200mv_0c.ddb
....\...........\.........\..\FPGA_DDS_4.tiscmp.slow_1200mv_85c.ddb
....\...........\.........\..\FPGA_DDS_4.tis_db_list.ddb
....\...........\.........\..\FPGA_DDS_4.tmw_info
....\...........\.........\..\logic_util_heursitic.dat
....\...........\.........\..\prev_cmp_FPGA_DDS_4.asm.qmsg
....\...........\.........\..\p