文件名称:Verilog_digital_clock
- 所属分类：
- VHDL编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2014-05-14
- 文件大小：
- 1.92mb
- 下载次数：
- 0次
- 提 供 者：
- huyun*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
Digital clock using Quartus9.1 platform, using Verilog language, to share to everyone
(系统自动生成,下载前可以参看下载内容)
下载文件列表
数字钟设计
..........\clock.asm.rpt
..........\clock.done
..........\clock.fit.rpt
..........\clock.fit.smsg
..........\clock.fit.summary
..........\clock.flow.rpt
..........\clock.map.rpt
..........\clock.map.smsg
..........\clock.map.summary
..........\clock.pin
..........\clock.qpf
..........\clock.qsf
..........\clock.qws
..........\clock.sof
..........\clock.sta.rpt
..........\clock.sta.summary
..........\clock.v
..........\clock.v.bak
..........\db
..........\..\clock.asm.qmsg
..........\..\clock.asm.rdb
..........\..\clock.asm_labs.ddb
..........\..\clock.cbx.xml
..........\..\clock.cmp.bpm
..........\..\clock.cmp.cbp
..........\..\clock.cmp.cdb
..........\..\clock.cmp.ecobp
..........\..\clock.cmp.hdb
..........\..\clock.cmp.kpt
..........\..\clock.cmp.logdb
..........\..\clock.cmp.rdb
..........\..\clock.cmp_merge.kpt
..........\..\clock.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
..........\..\clock.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
..........\..\clock.db_info
..........\..\clock.eco.cdb
..........\..\clock.fit.qmsg
..........\..\clock.hier_info
..........\..\clock.hif
..........\..\clock.lpc.html
..........\..\clock.lpc.rdb
..........\..\clock.lpc.txt
..........\..\clock.map.bpm
..........\..\clock.map.cdb
..........\..\clock.map.ecobp
..........\..\clock.map.hdb
..........\..\clock.map.kpt
..........\..\clock.map.logdb
..........\..\clock.map.qmsg
..........\..\clock.map_bb.cdb
..........\..\clock.map_bb.hdb
..........\..\clock.map_bb.logdb
..........\..\clock.pre_map.cdb
..........\..\clock.pre_map.hdb
..........\..\clock.rtlv.hdb
..........\..\clock.rtlv_sg.cdb
..........\..\clock.rtlv_sg_swap.cdb
..........\..\clock.sgdiff.cdb
..........\..\clock.sgdiff.hdb
..........\..\clock.sld_design_entry.sci
..........\..\clock.sld_design_entry_dsc.sci
..........\..\clock.smart_action.txt
..........\..\clock.sta.qmsg
..........\..\clock.sta.rdb
..........\..\clock.sta_cmp.8_slow_1200mv_85c.tdb
..........\..\clock.syn_hier_info
..........\..\clock.tiscmp.fastest_slow_1200mv_0c.ddb
..........\..\clock.tiscmp.fastest_slow_1200mv_85c.ddb
..........\..\clock.tiscmp.fast_1200mv_0c.ddb
..........\..\clock.tiscmp.slow_1200mv_0c.ddb
..........\..\clock.tiscmp.slow_1200mv_85c.ddb
..........\..\clock.tis_db_list.ddb
..........\..\clock.tmw_info
..........\..\logic_util_heursitic.dat
..........\..\prev_cmp_clock.map.qmsg
..........\..\prev_cmp_clock.qmsg
..........\incremental_db
..........\..............\compiled_partitions
..........\..............\...................\clock.root_partition.cmp.cdb
..........\..............\...................\clock.root_partition.cmp.dfp
..........\..............\...................\clock.root_partition.cmp.hdb
..........\..............\...................\clock.root_partition.cmp.kpt
..........\..............\...................\clock.root_partition.cmp.logdb
..........\..............\...................\clock.root_partition.cmp.rcfdb
..........\..............\...................\clock.root_partition.cmp.re.rcfdb
..........\..............\...................\clock.root_partition.map.cdb
..........\..............\...................\clock.root_partition.map.dpi
..........\..............\...................\clock.root_partition.map.hdb
..........\..............\...................\clock.root_partition.map.kpt
..........\..............\README