文件名称:zedB_gpio_vga
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xilinx zynq7000开发板SDK工程实例，对于用于嵌入式开发很有指导价值。-Xilinx zynq7000 development board SDK project example, having guiding value for embedded development
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下载文件列表
zedB_gpio_vga
.............\clock_generator_0.log
.............\data
.............\....\ps7_constraints.ucf
.............\....\ps7_constraints.xdc
.............\....\ps7_system_prj.xml
.............\....\system.ucf
.............\....\system.ucf~
.............\drivers
.............\.......\pwm_ip_v1_04_a
.............\.......\..............\data
.............\.......\..............\....\pwm_ip_v2_1_0.mdd
.............\.......\..............\....\pwm_ip_v2_1_0.tcl
.............\.......\..............\src
.............\.......\..............\...\Makefile
.............\.......\..............\...\pwm_ip.c
.............\.......\..............\...\pwm_ip.h
.............\.......\..............\...\pwm_ip_selftest.c
.............\.......\pwm_ip_v2_00_a
.............\.......\..............\data
.............\.......\..............\....\pwm_ip_v2_1_0.mdd
.............\.......\..............\....\pwm_ip_v2_1_0.tcl
.............\.......\..............\src
.............\.......\..............\...\Makefile
.............\.......\..............\...\pwm_ip.c
.............\.......\..............\...\pwm_ip.h
.............\.......\..............\...\pwm_ip_selftest.c
.............\etc
.............\...\bitgen.ut
.............\...\download.cmd
.............\...\fast_runtime.opt
.............\...\system.filters
.............\...\system.gui
.............\implementation
.............\..............\system_summary.html
.............\pcores
.............\......\axi_clkgen_v1_00_a
.............\......\..................\.svn
.............\......\..................\....\entries
.............\......\..................\....\format
.............\......\..................\....\pristine
.............\......\..................\....\........\04
.............\......\..................\....\........\..\04625192e466cb62dfec63a4a36924f70c2a8bc5.svn-base
.............\......\..................\....\........\34
.............\......\..................\....\........\..\34d45f49fd468a2bfa0d0d6c2bd1372e93940856.svn-base
.............\......\..................\....\........\46
.............\......\..................\....\........\..\46684f3848005f67348e73d70cdaf599bd7659ef.svn-base
.............\......\..................\....\........\50
.............\......\..................\....\........\..\505ef147081c00df706de0fd0374c2f4804e19dc.svn-base
.............\......\..................\....\........\a7
.............\......\..................\....\........\..\a793ef7feeff35ec6898a3687c0b828945ffbb67.svn-base
.............\......\..................\....\........\f0
.............\......\..................\....\........\..\f0d779f4cacbf7048a6b2f6a438df665d83c22c4.svn-base
.............\......\..................\....\tmp
.............\......\..................\....\...\prop-base
.............\......\..................\....\...\props
.............\......\..................\....\...\text-base
.............\......\..................\....\wc.db
.............\......\..................\data
.............\......\..................\....\axi_clkgen_v2_1_0.mpd
.............\......\..................\....\axi_clkgen_v2_1_0.pao
.............\......\..................\....\_axi_clkgen_xst.prj
.............\......\..................\hdl
.............\......\..................\...\verilog
.............\......\..................\...\.......\cf_clkgen.v
.............\......\..................\...\.......\user_logic.v
.............\......\..................\...\vhdl
.............\......\..................\...\....\axi_clkgen.vhd
.............\......\axi_hdmi_tx_16b_v1_00_a
.............\......\.......................\data
.............\......\.......................\....\axi_hdmi_tx_16b_v2_1_0.mpd
.............\......\.......................\....\axi_hdmi_tx_16b_v2_1_0.pao
.............\......\.......................\....\_axi_hdmi_tx_16b_xst.prj
.............\......\.......................\hdl
.............\......\.......................\...\verilog
.............\......\.......................\...\.......\cf_add.v
.............\......\.......................\...\.......\cf_csc_1.v
......