文件名称:IPCores_iic_8051
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I2C_IP_Core, 使用VHDL 和VERLOG编写，并有文档说明-I2C IP Core, VHDL/Verilog
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下载文件列表
jtag\tap\doc\jtag.pdf
....\...\...\src\jtag.doc
....\...\...\src
....\...\doc
....\...\rtl\verilog\tap_defines.v
....\...\...\.......\tap_top.v
....\...\...\verilog
....\...\rtl
....\tap
jtag
vgalcd\vga_lcd\bench\verilog\sync_check.v
......\.......\.....\.......\tests.v
......\.......\.....\.......\test_bench_top.v
......\.......\.....\.......\wb_b3_check.v
......\.......\.....\.......\wb_mast_model.v
......\.......\.....\.......\wb_model_defines.v
......\.......\.....\.......\wb_slv_model.v
......\.......\.....\verilog
......\.......\bench
......\.......\doc\src\vga_core_enh.doc
......\.......\...\src
......\.......\...\vga_core.pdf
......\.......\doc
......\.......\rtl\verilog\generic_dpram.v
......\.......\...\.......\generic_spram.v
......\.......\...\.......\timescale.v
......\.......\...\.......\vga_clkgen.v
......\.......\...\.......\vga_colproc.v
......\.......\...\.......\vga_csm_pb.v
......\.......\...\.......\vga_curproc.v
......\.......\...\.......\vga_cur_cregs.v
......\.......\...\.......\vga_defines.v
......\.......\...\.......\vga_enh_top.v
......\.......\...\.......\vga_fifo.v
......\.......\...\.......\vga_fifo_dc.v
......\.......\...\.......\vga_pgen.v
......\.......\...\.......\vga_tgen.v
......\.......\...\.......\vga_vtim.v
......\.......\...\.......\vga_wb_master.v
......\.......\...\.......\vga_wb_slave.v
......\.......\...\verilog
......\.......\...\.hdl\colproc.vhd
......\.......\...\....\counter.vhd
......\.......\...\....\csm_pb.vhd
......\.......\...\....\dpm.vhd
......\.......\...\....\fifo.vhd
......\.......\...\....\fifo_dc.vhd
......\.......\...\....\pgen.vhd
......\.......\...\....\tgen.vhd
......\.......\...\....\vga.vhd
......\.......\...\....\vga_and_clut.vhd
......\.......\...\....\vga_and_clut_tstbench.vhd
......\.......\...\....\vtim.vhd
......\.......\...\....\wb_master.vhd
......\.......\...\....\wb_slave.vhd
......\.......\...\vhdl
......\.......\rtl
......\.......\sim\rtl_sim\bin\Makefile
......\.......\...\.......\bin
......\.......\...\.......\run
......\.......\...\rtl_sim
......\.......\sim
......\.......\.oftware\drivers
......\.......\........\include\oc_vga_lcd.h
......\.......\........\include
......\.......\software
......\.......\.yn\bin\comp.dc
......\.......\...\...\design_spec.dc
......\.......\...\...\lib_spec.dc
......\.......\...\...\read.dc
......\.......\...\bin
......\.......\...\log
......\.......\...\out
......\.......\...\run
......\.......\syn
......\vga_lcd
vgalcd
WISHBONE Interconnect Matrix IP CORE\wb_conmax\bench\verilog\tests.v
....................................\.........\.....\.......\test_bench_top.v
....................................\.........\.....\.......\wb_mast_model.v
....................................\.........\.....\.......\wb_model_defines.v
....................................\.........\.....\.......\wb_slv_model.v
....................................\.........\.....\verilog
....................................\.........\bench
....................................\.........\doc\conmax.pdf
....................................\.........\...\README.txt
....................................\.........\...\STATUS.txt
....................................\.........\doc
....................................\.........\rtl\verilog\wb_conmax_arb.v
....................................\.........\...\.......\wb_conmax_defines.v
....................................\.........\...\.......\wb_conmax_master_if.v
....................................\.........\...\.......\wb_conmax_msel.v
....................................\.........\...\.......\wb_conmax_pri_dec.v
....................................\.........\...\.......\wb_conmax_pri_enc.v
....................................\.........\...\.......\wb_conmax_rf.v
....................................\.........\...\.......\wb_conmax_slave_if.v
....................................\.........\...\.......\wb_conmax_top.v
....................................\.........\...\verilog
....................................\.........\rtl
....................................\.........\sim\rtl_sim\bin\Makefile