文件名称:labs_system_verilog_testbench

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [C/C++] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 70kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 李*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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system verilog testbench 对应代码。-labs for system verilog testbench
(系统自动生成,下载前可以参看下载内容)

下载文件列表





ces_svtb_2011.12\.setup.modules

................\.testMaster\Driver.sv

................\...........\DriverBase.sv

................\...........\Generator.sv

................\...........\Makefile

................\...........\Packet.sv

................\...........\Receiver.sv

................\...........\ReceiverBase.sv

................\...........\router.if.sv

................\...........\router.tb.sv

................\...........\router.test_top.sv

................\...........\router.v

................\...........\Scoreboard.sv

................\...........\test.sv

................\.testscript

................\labs\lab1\Makefile

................\....\....\router_io.sv

................\....\....\router_test_top.sv

................\....\....\test.sv

................\....\...2\Makefile

................\....\...3\Makefile

................\....\...4\Makefile

................\....\...5\Makefile

................\....\...6\Makefile

................\README

................\rtl\bad\router.v

................\...\router.v

................\solutions\lab1\Makefile

................\.........\....\router_io.sv

................\.........\....\router_io.sv.orig

................\.........\....\router_test_top.sv

................\.........\....\router_test_top.sv.orig

................\.........\....\test.sv

................\.........\....\test.sv.orig

................\.........\...2\Makefile

................\.........\....\router_io.sv

................\.........\....\router_test_top.sv

................\.........\....\test.sv

................\.........\....\test.sv.orig

................\.........\...3\Makefile

................\.........\....\router_io.sv

................\.........\....\router_test_top.sv

................\.........\....\test.sv

................\.........\....\test.sv.orig

................\.........\...4\.display

................\.........\....\Makefile

................\.........\....\Packet.sv

................\.........\....\Packet.sv.orig

................\.........\....\router_io.sv

................\.........\....\router_test_top.sv

................\.........\....\test.sv

................\.........\....\test.sv.orig

................\.........\...5\Driver.sv

................\.........\....\Driver.sv.orig

................\.........\....\DriverBase.sv

................\.........\....\Generator.sv

................\.........\....\Makefile

................\.........\....\Packet.sv

................\.........\....\Receiver.sv

................\.........\....\Receiver.sv.orig

................\.........\....\ReceiverBase.sv

................\.........\....\router_io.sv

................\.........\....\router_test.h

................\.........\....\router_test_top.sv

................\.........\....\Scoreboard.sv

................\.........\....\test.sv

................\.........\....\test.sv.orig

................\.........\...6\Driver.sv

................\.........\....\DriverBase.sv

................\.........\....\Environment.sv

................\.........\....\Generator.sv

................\.........\....\Makefile

................\.........\....\Packet.sv

................\.........\....\Receiver.sv

................\.........\....\ReceiverBase.sv

................\.........\....\router_io.sv

................\.........\....\router_test.h

................\.........\....\router_test_pkg.sv

................\.........\....\router_test_pkg.sv.orig

................\.........\....\router_test_top.sv

................\.........\....\Scoreboard.sv

................\.........\....\Scoreboard.sv.orig

................\.........\....\test.sv

................\.........\....\test.sv.orig

................\labs\lab1

................\....\lab2

................\....\lab3

................\....\lab4

................\....\lab5

................\....\lab6

................\rtl\bad

................\solutions\lab1

................\.........\lab2

................\.........\lab3

................\.........\lab4

................\.........\lab5

................\.........\lab6

................\.testMaster

................\labs

................\rtl

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