文件名称:DE2_NET

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [C/C++] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.74mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 余**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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基于altera的DE2开发板的以太网设计成功例程-Successful routine altera DE2 board Ethernet design




(系统自动生成,下载前可以参看下载内容)

下载文件列表

DE2_NET\.metadata\.lock

.......\.........\.log

.......\.........\.plugins\org.eclipse.cdt.core\.log

.......\.........\........\....................\hello_led_0.1182493160437.pdom

.......\.........\........\....................\hello_led_0_syslib.1182493161265.pdom

.......\.........\........\................make.core\specs.c

.......\.........\........\.........................\specs.cpp

.......\.........\........\.............ore.resources\.projects\hello_led_0\.indexes\properties.index

.......\.........\........\..........................\.........\...........\.properties

.......\.........\........\..........................\.........\..........._syslib\.indexes\properties.index

.......\.........\........\..........................\.........\..................\.properties

.......\.........\........\..........................\.root\.indexes\history.version

.......\.........\........\..........................\.....\........\properties.index

.......\.........\........\..........................\.....\........\properties.version

.......\.........\........\..........................\.....\16.tree

.......\.........\........\..........................\.safetable\org.eclipse.core.resources

.......\.........\........\..................untime\.settings\org.eclipse.cdt.core.prefs

.......\.........\........\........................\.........\org.eclipse.cdt.debug.core.prefs

.......\.........\........\........................\.........\org.eclipse.cdt.managedbuilder.core.prefs

.......\.........\........\........................\.........\org.eclipse.cdt.ui.prefs

.......\.........\........\........................\.........\org.eclipse.core.resources.prefs

.......\.........\........\........................\.........\org.eclipse.team.cvs.ui.prefs

.......\.........\........\........................\.........\org.eclipse.team.ui.prefs

.......\.........\........\........................\.........\org.eclipse.ui.ide.prefs

.......\.........\........\........................\.........\org.eclipse.ui.prefs

.......\.........\........\........................\.........\org.eclipse.ui.workbench.prefs

.......\.........\........\............debug.core\.launches\hello_led_0 Nios II HW configuration.launch

.......\.........\........\..................ui\dialog_settings.xml

.......\.........\........\....................\launchConfigurationHistory.xml

.......\.........\........\............team.ui\syncParticipants.xml

.......\.........\........\............ui.ide\dialog_settings.xml

.......\.........\........\...............workbench\dialog_settings.xml

.......\.........\........\........................\workbench.xml

.......\.........\version.ini

.......\.sopc_builder\install.ptf

.......\.............\install2.ptf

.......\altpllpll_0.ppf

.......\Audio_0.v

.......\......DAC_FIFO\cb_generator.pl

.......\..............\class.ptf

.......\..............\hdl\AUDIO_DAC_FIFO.v

.......\..............\...\FIFO_16_256.v

.......\AUDIO_DAC_FIFO.v

.......\Audio_PLL.ppf

.......\Audio_PLL.v

.......\bht_ram.mif

.......\Binary_VGA_Controller\cb_generator.pl

.......\.....................\class.ptf

.......\.....................\hdl\Img_DATA.hex

.......\.....................\...\Img_RAM.v

.......\.....................\...\VGA_Controller.v

.......\.....................\...\VGA_NIOS_CTRL.v

.......\.....................\...\VGA_OSD_RAM.v

.......\.....................\...\VGA_Param.h

.......\.....................\inc\VGA.c

.......\.....................\...\VGA.h

.......\button_pio.v

.......\clock_0.v

.......\clock_1.v

.......\cpu_0.ocp

.......\cpu_0.v

.......\cpu_0.vo

.......\cpu_0_bht_ram.mif

.......\cpu_0_dc_tag_ram.mif

.......\cpu_0_ic_tag_ram.mif

.......\cpu_0_jtag_debug_module.v

.......\cpu_0_jtag_debug_module_wrapper.v

.......\cpu_0_mult_cell.v

.......\cpu_0_ociram_default_contents.mif

.......\cpu_0_rf_ram_a.mif

.......\cpu_0_rf_ram_b.mif

.......\cpu_0_test_bench.v

.......\dc_tag_ram.mif

.......\DE2_Board\class.ptf

.......\.........\system\.sopc_builder\install.ptf

.......\.........\......\asmi.v

.......\.........\......\cmp_state.ini

.......\.........\......\cpu_0.

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