文件名称:mpci32-verilog
介绍说明－－下载内容均来自于网络，请自行研究使用
一个32BIT 33/66MHz PCI CORE，verilog 的RTL CODEs-pci ipcore writen by verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
verilog\gates\synop\mpci.sdf
.......\.....\.....\mpci.v
.......\.....\.....\synop.readme
.......\rtl\bidir.v
.......\...\cmd.bat
.......\...\ibuf.v
.......\...\m3s010ds.v
.......\...\m3s011ds.v
.......\...\m3s013ds.v
.......\...\m3s016ds.v
.......\...\m3s017ds.v
.......\...\m3s018ds.v
.......\...\m3s019ds.v
.......\...\m3s020ds.v
.......\...\m3s021ds.v
.......\...\m3s022ds.v
.......\...\m3s023ds.v
.......\...\m3s024ds.v
.......\...\m3s025ds.v
.......\...\m3s026ds.v
.......\...\m3s027ds.v
.......\...\m3s040ds.v
.......\...\m3s041ds.v
.......\...\m3s042ds.v
.......\...\m3s044ds.v
.......\...\m3s050ds.v
.......\...\m3s051ds.v
.......\...\m3s052ds.v
.......\...\m3s070ds.v
.......\...\m3s071ds.v
.......\...\m3s072ds.v
.......\...\m3s080ds.v
.......\...\m3s101ds.v
.......\...\m3s102ds.v
.......\...\m3s115ds.v
.......\...\m3s119ds.v
.......\...\m3s121ds.v
.......\...\mpci.v
.......\...\mpci_io.v
.......\...\mpci_io_gate.v
.......\...\tbuf.v
.......\sim\arbiter.v
.......\...\arbiter_switch.v
.......\...\checker.v
.......\...\comp.all
.......\...\compg.all
.......\...\core_compile.scr
.......\...\core_config_reg.v
.......\...\core_cstschg_reg.v
.......\...\core_master.v
.......\...\core_target_fifo.v
.......\...\core_target_reg.v
.......\...\CSTSCHG_Test_Pkg.v
.......\...\gate_compile.scr
.......\...\main_testbench.v
.......\...\masterdiff.scr
.......\...\master_model.v
.......\...\modelsim.ini
.......\...\mpci_tb.v
.......\...\msim_gate.scr
.......\...\msim_gate_c.scr
.......\...\msim_rtl.scr
.......\...\msim_rtl_c.scr
.......\...\pcimon.v
.......\...\PCI_64Bit_Pkg.v
.......\...\PCI_backend_config_Pkg.v
.......\...\PCI_Compliance_Pkg.v
.......\...\PCI_Config_Pkg.v
.......\...\PCI_Tb_Prim_Proc_Pkg.v
.......\...\PCI_Types_Pkg.v
.......\...\PME_Test_Pkg.v
.......\...\pwr_mngmnt_model.v
.......\...\rtl_compile.scr
.......\...\sim.readme
.......\...\spi_prom_model.v
.......\...\SPI_Test_Pkg.v
.......\...\target0diff.scr
.......\...\target_model.v
.......\...\tb_compile.scr
.......\...\vxl_gate_c.scr
.......\...\vxl_rtl_c.scr
.......\...\wave.do
.......\.ynth\mgc\dft\dft.readme
.......\.....\...\...\dft_ad.do
.......\.....\...\...\dft_ad.scr
.......\.....\...\...\fscan.do
.......\.....\...\...\fscan.scr
.......\.....\synop\.synopsys_dc.setup
.......\.....\.....\hier_compile.scr
.......\.....\.....\hier_scan.scr
.......\.....\.....\hier_setup.scr
.......\.....\.....\scan.scr
.......\.....\.....\sedfix
.......\.....\.....\synth.readme
.......\.....\.....\synth.scr
.......\temp_sim\Debussy.exeLog\compiler.log
.......\........\..............\Debussy.exe.cmd
.......\........\..............\Debussy.exe.cmd.bak
.......\........\..............\novas.rc
.......\........\..............\ToNetlist.log
.......\.....\.....\mpci.v
.......\.....\.....\synop.readme
.......\rtl\bidir.v
.......\...\cmd.bat
.......\...\ibuf.v
.......\...\m3s010ds.v
.......\...\m3s011ds.v
.......\...\m3s013ds.v
.......\...\m3s016ds.v
.......\...\m3s017ds.v
.......\...\m3s018ds.v
.......\...\m3s019ds.v
.......\...\m3s020ds.v
.......\...\m3s021ds.v
.......\...\m3s022ds.v
.......\...\m3s023ds.v
.......\...\m3s024ds.v
.......\...\m3s025ds.v
.......\...\m3s026ds.v
.......\...\m3s027ds.v
.......\...\m3s040ds.v
.......\...\m3s041ds.v
.......\...\m3s042ds.v
.......\...\m3s044ds.v
.......\...\m3s050ds.v
.......\...\m3s051ds.v
.......\...\m3s052ds.v
.......\...\m3s070ds.v
.......\...\m3s071ds.v
.......\...\m3s072ds.v
.......\...\m3s080ds.v
.......\...\m3s101ds.v
.......\...\m3s102ds.v
.......\...\m3s115ds.v
.......\...\m3s119ds.v
.......\...\m3s121ds.v
.......\...\mpci.v
.......\...\mpci_io.v
.......\...\mpci_io_gate.v
.......\...\tbuf.v
.......\sim\arbiter.v
.......\...\arbiter_switch.v
.......\...\checker.v
.......\...\comp.all
.......\...\compg.all
.......\...\core_compile.scr
.......\...\core_config_reg.v
.......\...\core_cstschg_reg.v
.......\...\core_master.v
.......\...\core_target_fifo.v
.......\...\core_target_reg.v
.......\...\CSTSCHG_Test_Pkg.v
.......\...\gate_compile.scr
.......\...\main_testbench.v
.......\...\masterdiff.scr
.......\...\master_model.v
.......\...\modelsim.ini
.......\...\mpci_tb.v
.......\...\msim_gate.scr
.......\...\msim_gate_c.scr
.......\...\msim_rtl.scr
.......\...\msim_rtl_c.scr
.......\...\pcimon.v
.......\...\PCI_64Bit_Pkg.v
.......\...\PCI_backend_config_Pkg.v
.......\...\PCI_Compliance_Pkg.v
.......\...\PCI_Config_Pkg.v
.......\...\PCI_Tb_Prim_Proc_Pkg.v
.......\...\PCI_Types_Pkg.v
.......\...\PME_Test_Pkg.v
.......\...\pwr_mngmnt_model.v
.......\...\rtl_compile.scr
.......\...\sim.readme
.......\...\spi_prom_model.v
.......\...\SPI_Test_Pkg.v
.......\...\target0diff.scr
.......\...\target_model.v
.......\...\tb_compile.scr
.......\...\vxl_gate_c.scr
.......\...\vxl_rtl_c.scr
.......\...\wave.do
.......\.ynth\mgc\dft\dft.readme
.......\.....\...\...\dft_ad.do
.......\.....\...\...\dft_ad.scr
.......\.....\...\...\fscan.do
.......\.....\...\...\fscan.scr
.......\.....\synop\.synopsys_dc.setup
.......\.....\.....\hier_compile.scr
.......\.....\.....\hier_scan.scr
.......\.....\.....\hier_setup.scr
.......\.....\.....\scan.scr
.......\.....\.....\sedfix
.......\.....\.....\synth.readme
.......\.....\.....\synth.scr
.......\temp_sim\Debussy.exeLog\compiler.log
.......\........\..............\Debussy.exe.cmd
.......\........\..............\Debussy.exe.cmd.bak
.......\........\..............\novas.rc
.......\........\..............\ToNetlist.log