文件名称:32bit-RISC-CPU-IP
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使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction pre-judgment and interrupt handling functions for Verilog language learners in depth reference.
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下载文件列表
32bit RISC CPU IP\potato_verilog\alu.v
.................\..............\cntrl_rf.v
.................\..............\cpu.v
.................\..............\decode.v
.................\..............\forward.v
.................\..............\interrupt.v
.................\..............\mpu.v
.................\..............\pc_gen.v
.................\..............\ram.v
.................\..............\regfile.v
.................\..............\reg_ex.v
.................\..............\reg_id.v
.................\..............\reg_if.v
.................\..............\reg_mem.v
.................\..............\rom.v
.................\..............\write_back.v
.................\约束文件.doc
.................\potato_verilog
32bit RISC CPU IP
.................\..............\cntrl_rf.v
.................\..............\cpu.v
.................\..............\decode.v
.................\..............\forward.v
.................\..............\interrupt.v
.................\..............\mpu.v
.................\..............\pc_gen.v
.................\..............\ram.v
.................\..............\regfile.v
.................\..............\reg_ex.v
.................\..............\reg_id.v
.................\..............\reg_if.v
.................\..............\reg_mem.v
.................\..............\rom.v
.................\..............\write_back.v
.................\约束文件.doc
.................\potato_verilog
32bit RISC CPU IP