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文件名称:MyDDR

  • 所属分类：
  • VHDL编程
  • 资源属性：
  • [PDF]
  • 上传时间：
  • 2012-11-26
  • 文件大小：
  • 8.99mb
  • 下载次数：
  • 0次
  • 提 供 者：
  • DM***
  • 相关连接：
  • 无
  • 下载说明：
  • 别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容均来自于网络，请自行研究使用

分析FPGA如何控制DDR，这个方法是自己倍频而不是把倍频过程放进IPCORE里面处理-Analysis of how to control the FPGA DDR, this method is its frequency multiplier rather than the process inside the handle into the IPCORE
(系统自动生成,下载前可以参看下载内容)

下载文件列表

MyDDR\coregen_xil_3800_28.cgc

.....\coregen_xil_3800_28.cgp

.....\ddrm1.vhd

.....\ipcore_dir\coregen.cgc

.....\..........\coregen.cgp

.....\..........\coregen.log

.....\..........\coregen.rsp

.....\..........\DDRCtrl\docs\768c.pdf

.....\..........\.......\....\adr_cntrl_timing_0.xls

.....\..........\.......\....\read_data_timing_0.xls

.....\..........\.......\....\ug086.pdf

.....\..........\.......\....\write_data_timing_0.xls

.....\..........\.......\example_design\datasheet.txt

.....\..........\.......\..............\log.txt

.....\..........\.......\..............\mig.prj

.....\..........\.......\..............\par\create_ise.bat

.....\..........\.......\..............\...\DDRCtrl.ucf

.....\..........\.......\..............\...\icon_coregen.xco

.....\..........\.......\..............\...\ila_coregen.xco

.....\..........\.......\..............\...\ise_flow.bat

.....\..........\.......\..............\...\ise_run.txt

.....\..........\.......\..............\...\makeproj.bat

.....\..........\.......\..............\...\mem_interface_top.ut

.....\..........\.......\..............\...\readme.txt

.....\..........\.......\..............\...\rem_files.bat

.....\..........\.......\..............\...\set_ise_prop.tcl

.....\..........\.......\..............\...\vio_coregen.xco

.....\..........\.......\..............\rtl\DDRCtrl.vhd

.....\..........\.......\..............\...\DDRCtrl_addr_gen_0.vhd

.....\..........\.......\..............\...\DDRCtrl_cal_ctl.vhd

.....\..........\.......\..............\...\DDRCtrl_cal_top.vhd

.....\..........\.......\..............\...\DDRCtrl_cmd_fsm_0.vhd

.....\..........\.......\..............\...\DDRCtrl_cmp_data_0.vhd

.....\..........\.......\..............\...\DDRCtrl_controller_0.vhd

.....\..........\.......\..............\...\DDRCtrl_controller_iobs_0.vhd

.....\..........\.......\..............\...\DDRCtrl_data_gen_0.vhd

.....\..........\.......\..............\...\DDRCtrl_data_path_0.vhd

.....\..........\.......\..............\...\DDRCtrl_data_path_iobs_0.vhd

.....\..........\.......\..............\...\DDRCtrl_data_read_0.vhd

.....\..........\.......\..............\...\DDRCtrl_data_read_controller_0.vhd

.....\..........\.......\..............\...\DDRCtrl_data_write_0.vhd

.....\..........\.......\..............\...\DDRCtrl_dqs_delay_0.vhd

.....\..........\.......\..............\...\DDRCtrl_fifo_0_wr_en_0.vhd

.....\..........\.......\..............\...\DDRCtrl_fifo_1_wr_en_0.vhd

.....\..........\.......\..............\...\DDRCtrl_infrastructure.vhd

.....\..........\.......\..............\...\DDRCtrl_infrastructure_iobs_0.vhd

.....\..........\.......\..............\...\DDRCtrl_infrastructure_top0.vhd

.....\..........\.......\..............\...\DDRCtrl_iobs_0.vhd

.....\..........\.......\..............\...\DDRCtrl_main_0.vhd

.....\..........\.......\..............\...\DDRCtrl_parameters_0.vhd

.....\..........\.......\..............\...\DDRCtrl_ram8d_0.vhd

.....\..........\.......\..............\...\DDRCtrl_rd_gray_cntr.vhd

.....\..........\.......\..............\...\DDRCtrl_s3_dm_iob.vhd

.....\..........\.......\..............\...\DDRCtrl_s3_dqs_iob.vhd

.....\..........\.......\..............\...\DDRCtrl_s3_dq_iob.vhd

.....\..........\.......\..............\...\DDRCtrl_tap_dly.vhd

.....\..........\.......\..............\...\DDRCtrl_test_bench_0.vhd

.....\..........\.......\..............\...\DDRCtrl_top_0.vhd

.....\..........\.......\..............\...\DDRCtrl_wr_gray_cntr.vhd

.....\..........\.......\..............\sim\ddr_model.v

.....\..........\.......\..............\...\ddr_model_parameters.vh

.....\..........\.......\..............\...\sim.do

.....\..........\.......\..............\...\sim_tb_top.vhd

.....\..........\.......\..............\...\wiredly.vhd

.....\..........\.......\..............\.ynth\DDRCtrl.lso

.....\..........\.......\..............\.....\DDRCtrl.prj

.....\..........\.......\..............\.....\mem_interface_top_synp.sdc

.....\..........\.......\..............\.....\script_synp.tcl

.....\..........\.......\user_design\datasheet.txt

.....\..........\.......\...........\log.

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