文件名称:uart2bus
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uart接口到内部总线的IP核，采用VDHL和VERILOG语言编写。-UART interface to Bus IP Core in VHDL and verilog languages
(系统自动生成,下载前可以参看下载内容)
下载文件列表
scilab\calc_baud_gen.sce
verilog\sim\icarus\gtk.bat
.......\...\......\compile_bin.bat
.......\...\......\block_bin.cfg
.......\...\......\block_txt.cfg
.......\...\......\test.bin
.......\...\......\compile_txt.bat
.......\...\......\run.bat
.......\...\......\test.txt
.......\bench\timescale.v
.......\.....\tb_uart2bus_top.v
.......\.....\tb_txt_uart2bus_top.v
.......\.....\uart_tasks.v
.......\.....\reg_file_model.v
.......\.....\tb_bin_uart2bus_top.v
.......\syn\altera\uart2bus_top.qsf
.......\...\......\uart2bus.qpf
.......\...\......\uart2bus.qws
.......\...\xilinx\uart2bus.xise
.......\rtl\uart2bus_top.v
.......\...\uart_rx.v
.......\...\uart_top.v
.......\...\uart_tx.v
.......\...\uart_parser.v
.......\...\baud_gen.v
.hdl\test.bin
....\bench\uart2BusTop_bin_tb.vhd
....\.....\uart2BusTop_txt_tb.vhd
....\.....\regFileModel.vhd
....\syn\xilinx\uart2bus.xise
....\rtl\uart2BusTop.vhd
....\...\uartTop.vhd
....\...\uartParser.vhd
....\...\uartTx.vhd
....\...\uartRx.vhd
....\...\baudGen.vhd
....\test.txt
.erilog\sim\icarus
.......\.yn\altera
.......\...\xilinx
.hdl\sim\modelsim
....\.yn\xilinx
.erilog\sim
.......\bench
.......\syn
.......\rtl
.hdl\sim
....\bench
....\syn
....\rtl
scilab
verilog
vhdl
verilog\sim\icarus\gtk.bat
.......\...\......\compile_bin.bat
.......\...\......\block_bin.cfg
.......\...\......\block_txt.cfg
.......\...\......\test.bin
.......\...\......\compile_txt.bat
.......\...\......\run.bat
.......\...\......\test.txt
.......\bench\timescale.v
.......\.....\tb_uart2bus_top.v
.......\.....\tb_txt_uart2bus_top.v
.......\.....\uart_tasks.v
.......\.....\reg_file_model.v
.......\.....\tb_bin_uart2bus_top.v
.......\syn\altera\uart2bus_top.qsf
.......\...\......\uart2bus.qpf
.......\...\......\uart2bus.qws
.......\...\xilinx\uart2bus.xise
.......\rtl\uart2bus_top.v
.......\...\uart_rx.v
.......\...\uart_top.v
.......\...\uart_tx.v
.......\...\uart_parser.v
.......\...\baud_gen.v
.hdl\test.bin
....\bench\uart2BusTop_bin_tb.vhd
....\.....\uart2BusTop_txt_tb.vhd
....\.....\regFileModel.vhd
....\syn\xilinx\uart2bus.xise
....\rtl\uart2BusTop.vhd
....\...\uartTop.vhd
....\...\uartParser.vhd
....\...\uartTx.vhd
....\...\uartRx.vhd
....\...\baudGen.vhd
....\test.txt
.erilog\sim\icarus
.......\.yn\altera
.......\...\xilinx
.hdl\sim\modelsim
....\.yn\xilinx
.erilog\sim
.......\bench
.......\syn
.......\rtl
.hdl\sim
....\bench
....\syn
....\rtl
scilab
verilog
vhdl