文件名称:lab1
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labs in verilog it consists of lab work from design of mux adders from primitives
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下载文件列表
lab1\rtl\.alu_8.v.swp
....\...\add_sub4.v
....\...\alu4.v
....\...\b2g.v
....\...\decoder3x8.v
....\...\eg1.v
....\...\encoder4x2.v
....\...\fulladder.v
....\...\g2b.v
....\...\multiplier.v
....\...\mux2_1.v
....\...\mux8_1.v
....\...\xor_3.v
....\rtl
lab1
....\...\add_sub4.v
....\...\alu4.v
....\...\b2g.v
....\...\decoder3x8.v
....\...\eg1.v
....\...\encoder4x2.v
....\...\fulladder.v
....\...\g2b.v
....\...\multiplier.v
....\...\mux2_1.v
....\...\mux8_1.v
....\...\xor_3.v
....\rtl
lab1