In recent years, due to rapid advances in VLSI manufacturing

technology capable of packing more and more devices and

wires on a chip, crosstalk has emerged as a serious problem

affecting circuit reliability. Even though FPGAs are more

immune to crosstalk noise than their ASIC counterparts

manufactured in the same technological process, we have

reached the point where FPGAs have become affected by

crosstalk as well. Because FPGAs have regular interconnect

structures, crosstalk noise can be more easily controlled. In

this paper, we investigate the crosstalk noise in FPGAs and

propose new strategies to reduce its impact on delay. Our

methods can reduce crosstalk noise by statistically significant

amounts with no penalty in performance, power, or area.