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文件名称:quaddecoder_verilog_ise11.2_used_09042010

  • 所属分类：
  • VHDL编程
  • 资源属性：
  • [VHDL] [源码]
  • 上传时间：
  • 2012-11-26
  • 文件大小：
  • 69kb
  • 下载次数：
  • 0次
  • 提 供 者：
  • J***
  • 相关连接：
  • 无
  • 下载说明：
  • 别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容均来自于网络，请自行研究使用

Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File.

The Pinout is descr ipted in the Constrained file quad.ucf.

To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant.

For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.-Two simple Quadrature decoder and Counter build in a XILINX　XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File.

The Pinout is descr ipted in the Constrained file quad.ucf.

To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz　(i use 1.8432Mhz and tested 32768Khz) works brilliant.

For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.　
相关搜索： xc9536
cpld
ttl
incremental
Quadrature
encoder
Veril
quadrature
decoder
Verilog
Radio
QuadDecoder
verilog

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下载文件列表

quaddecoder_verilog_ise11.2_used_09042010\main.v

.........................................\quad.ipf

.........................................\quad.jed.ok

.........................................\quad.rar

.........................................\quad.ucf

.........................................\quaddecoder_verilog_ise11.2.gise

.........................................\quaddecoder_verilog_ise11.2.ise

.........................................\quaddecoder_verilog_ise11.2.xise

.........................................\..........................._xdb\tmp\ise\version

.........................................\...............................\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject

.........................................\...............................\...\...\............\..................\.........\HDProject_StrTbl

.........................................\...............................\...\...\............\PnAutoRun\Scripts\RunOnce_tcl

.........................................\...............................\...\...\............\.........\.......\RunOnce_tcl_StrTbl

.........................................\...............................\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main

.........................................\...............................\...\...\............\................\................\dpm_project_main_StrTbl

.........................................\...............................\...\...\............\................Gui\CViewSelector

.........................................\...............................\...\...\............\...................\CViewSelector_StrTbl

.........................................\...............................\...\...\............\...................\File-SynthesisOnly

.........................................\...............................\...\...\............\...................\File-SynthesisOnly_StrTbl

.........................................\...............................\...\...\............\...................\Library-SynthesisOnly

.........................................\...............................\...\...\............\...................\Library-SynthesisOnly_StrTbl

.........................................\...............................\...\...\............\...................\Process-BehavioralSim-

.........................................\...............................\...\...\............\...................\Process-BehavioralSim-_StrTbl

.........................................\...............................\...\...\............\...................\Process-SynthesisOnly-

.........................................\...............................\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF

.........................................\...............................\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF_StrTbl

.........................................\...............................\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG

.........................................\...............................\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG_StrTbl

.........................................\...............................\...\...\............\...................\Process-SynthesisOnly-_StrTbl

.........................................\...............................\...\...\............\...................\Source-BehavioralSim-AutoCompile

.........................................\...............................\...\...\............\...................\Source-BehavioralSim-AutoCompile_StrTbl

.........................................\...............................\...\...\............\...................\Source-SynthesisOnly-AutoCompile

.........................................\...............................\...\...\............\...................\Source-SynthesisOnly-AutoCompile_StrTbl

.........................................\...............................\...\...\..........

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