文件名称:XilinxOneWireInterface
介绍说明－－下载内容均来自于网络，请自行研究使用
Xilinx公司的1 wire接口HDL源代码，可以用来读取1 wire的rom。-Xilinx Inc. 1 wire interface to HDL source code, can be used to read the 1 wire in the rom.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
README
vhdl\bitreg.vhd
....\bytereg.vhd
....\clk_div.vhd
....\crcreg.vhd
....\jcounter.vhd
....\onewire_iface.vhd
....\onewire_iface_syn.prj
....\onewire_master.vhd
....\shreg.vhd
....\TEST_ONEWIRE_IFACE.DO
....\TEST_ONEWIRE_IFACE.VHD
vhdl
.erilog\bitreg.v
.......\clk_div.v
.......\crcreg.v
.......\defines.v
.......\glbl.v
.......\jcnt1.v
.......\jcnt2.v
.......\onewire_iface.v
.......\onewire_iface_syn.prj
.......\onewire_master.v
.......\parallel_sn_data.v
.......\sr1.v
.......\sr2.v
.......\TEST_NO_SLAVE.do
.......\TEST_NO_SLAVE.v
.......\TEST_ONEWIRE_WITH_BAD_CRC.do
.......\TEST_ONEWIRE_WITH_BAD_CRC.v
.......\TEST_ONEWIRE_WITH_VALID_CRC.do
.......\TEST_ONEWIRE_WITH_VALID_CRC.v
.......\TEST_SLAVE_PRESENT.do
.......\TEST_SLAVE_PRESENT.v
verilog
xapp198[1].pdf
vhdl\bitreg.vhd
....\bytereg.vhd
....\clk_div.vhd
....\crcreg.vhd
....\jcounter.vhd
....\onewire_iface.vhd
....\onewire_iface_syn.prj
....\onewire_master.vhd
....\shreg.vhd
....\TEST_ONEWIRE_IFACE.DO
....\TEST_ONEWIRE_IFACE.VHD
vhdl
.erilog\bitreg.v
.......\clk_div.v
.......\crcreg.v
.......\defines.v
.......\glbl.v
.......\jcnt1.v
.......\jcnt2.v
.......\onewire_iface.v
.......\onewire_iface_syn.prj
.......\onewire_master.v
.......\parallel_sn_data.v
.......\sr1.v
.......\sr2.v
.......\TEST_NO_SLAVE.do
.......\TEST_NO_SLAVE.v
.......\TEST_ONEWIRE_WITH_BAD_CRC.do
.......\TEST_ONEWIRE_WITH_BAD_CRC.v
.......\TEST_ONEWIRE_WITH_VALID_CRC.do
.......\TEST_ONEWIRE_WITH_VALID_CRC.v
.......\TEST_SLAVE_PRESENT.do
.......\TEST_SLAVE_PRESENT.v
verilog
xapp198[1].pdf