文件名称:verilog_example
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九个verilog源码例子，包括寄存器，状态机等，含testbench-9 verilog source code examples, including registers, state machines, with testbench
(系统自动生成,下载前可以参看下载内容)
下载文件列表
15-1 10d-counter\counter.v
.................\tcounter.v
7-8-3bitadder\Adder1Bit.v
.............\Adder3Bit.v
.............\test.vec
.............\testbench.v
....4bitadder\bit4_adder.v
.............\tb_bit4adder.v
....s2p\s2p.v
.......\testbenchs2p.v
....testbench\proced_reg.v
.............\test_proced_reg.v
13-1 Moore_FSM\Moore_State.v
...2 Mealy_FSM\Mealy_State.v
...3 10010_FSM\MEALY-FSM.v
...............\MOORE-FSM.v
...............\tb_fsm.v
15-1 10d-counter
7-8-3bitadder
7-8-4bitadder
7-8-s2p
7-8-testbench
13-1 Moore_FSM
13-2 Mealy_FSM
13-3 10010_FSM
.................\tcounter.v
7-8-3bitadder\Adder1Bit.v
.............\Adder3Bit.v
.............\test.vec
.............\testbench.v
....4bitadder\bit4_adder.v
.............\tb_bit4adder.v
....s2p\s2p.v
.......\testbenchs2p.v
....testbench\proced_reg.v
.............\test_proced_reg.v
13-1 Moore_FSM\Moore_State.v
...2 Mealy_FSM\Mealy_State.v
...3 10010_FSM\MEALY-FSM.v
...............\MOORE-FSM.v
...............\tb_fsm.v
15-1 10d-counter
7-8-3bitadder
7-8-4bitadder
7-8-s2p
7-8-testbench
13-1 Moore_FSM
13-2 Mealy_FSM
13-3 10010_FSM